1. Technical Field
The present invention relates to a method and structure for dynamically blocking access of a request signal to a shared bus such that the request originates from a non real-time master and requests access to an address range of an address space.
2. Related Art
With a proliferation of highly integrated system-on-a-chip designs, the shared bus architecture that allows major functional units to communicate is commonly utilized. There are many different shared bus designs which fit into a few distinct topographies. A known approach in shared bus topography is for multiple masters to present requests to an arbiter of the shared bus for accessing an address range of an address space, such as an address space of a given slave device. The arbiter awards bus control to the highest priority request based on a request prioritization algorithm. As an example, a shared bus may include a Processor Local Bus (PLB), wherein the PLB is part a CoreConnect bus architecture of the International Business Machines Corporation (IBM).
The use of an arbiter presents a key problem for a bus architecture in which the arbiter has visibility only to requests when the requests are made and has no knowledge of requests to be made subsequently. With a PLB, for example, the arbitration is done on a request-by-request basis, and requests are honored on the basis of immediate priority according to the prioritization algorithm.
The aforementioned limited visibility of the arbiter presents a critical problem for real-time processing such as the real-time processing of video and audio decoders. Such real-time processing involves sequentially stacked multiple requests by real-time masters (e.g., video and audio decoders) for access to an address range of an address space, in competition with requests to the same address range by non real-time masters such as central processing units (CPUs). The multiple requests are stacked in internal queues of the real-time masters but the status of such internal queues are invisible to the arbiter of the shared bus to which the queued requests will subsequently be presented. Thus a relatively low-priority request originating from a non real-time master (e.g., a CPU) and visible to the arbiter may be granted by the arbiter while a much higher priority request from a real-time master (e.g., a video decoder) may be sitting in the real-time master""s internal queue. If such high priority requests from the video decoder are not processed within specified time limits, then an artifact instead of a real image will appear on a video screen. Accordingly, video and audio decoders need to process data on a real-time basis.
Thus, there is a need to limit access of requests from non-real time masters in deference to internally queued requests of real-time masters.
The present invention provides a digital system, comprising:
a request limiter having a blocking mechanism for blocking access of a request signal to a shared bus, wherein the request signal originates from a blockable master, wherein the request signal requests access by the blockable master to an address range A of an address space, and wherein the shared bus manages requests for access to the address space;
a real-time clock, wherein an instantaneous clock cycle of the real time clock is denoted by a clock cycle index K such that K is a non-negative integer; and
an algorithm capable of dynamically enabling and disabling the blocking mechanism, wherein the algorithm is coupled to the clock, wherein the algorithm includes a dependence on K, wherein the algorithm includes a dependence on a variable Q whose value is a function of Q1, Q2, . . . , and QI, wherein Qi (i=1, 2, . . . , I) denotes an internal queuing state of an ith controlling master Mi, and wherein I is a positive integer that denotes a total number of the controlling masters.
The present invention provides a method for dynamically blocking an access of a request signal R to a shared bus such that R originates from a blockable master and requests access to an address range A of an address space, comprising the steps of:
providing the blockable master;
providing the shared bus for managing requests for access to the address space;
providing a real-time clock whose instantaneous clock cycle is denoted by a clock cycle index K such that K is a non-negative integer;
providing I controlling masters denoted as M1, M2, . . . , and MI, wherein I is a positive integer that denotes a total number of the controlling masters, and wherein each Mi (i=1, 2, . . . , I) is interfaced with the shared bus such that Mi may transmit a request signal Ri to the shared bus for access to an address range Ai within the address space; and
interfacing a request limiter between the blockable master and the shared bus, wherein the request limiter includes a blocking mechanism capable of blocking said access of the request signal R to the shared bus, wherein the blocking mechanism functions in accordance with an algorithm, wherein the algorithm is coupled to the clock, wherein the algorithm includes a dependence on K, wherein the algorithm includes a dependence on a variable Q whose value is a function F of Q1, Q2, . . . , and QI, and wherein Qi denotes an internal queuing state of Mi (i=1, 2, . . . , I).
The present invention has the advantage of limiting access of requests from non-real time masters in deference to internally queued requests of real-time masters.